1. Field
The disclosed embodiments relate to power-management techniques for multi-core processor systems. More specifically, the disclosed embodiments relate to power-management techniques that facilitates high-frequency operation of processor cores in a multi-core processor system.
2. Related Art
Modern computer systems typically utilize multiple processors and/or processor cores to increase computational performance. Processors in a multiprocessor system may additionally be configured to run at various speeds through a power management system that feeds different operating voltages and/or frequencies into the processors. For example, a four-core processor system with two idle cores may temporarily overclock the two non-idle cores by allocating power normally used to operate the idle cores to the non-idle cores.
However, the high-frequency execution of non-idle cores in a multi-core processor system may be limited by the subsequent asynchronous execution of the idle cores. For example, a timer queue for an idle core may include an asynchronous wakeup event that causes the core to resume operation at a pre-specified time in the future. If the core resumes operation during high-frequency operation of other cores in the multi-core processor system, the additional power required to resume execution of the core at high frequency may overload the power supply for the multi-core processor system, and in turn, cause the multi-core processor system to fail. To prevent such failure, overclocking of non-idle cores may be avoided whenever idle cores are associated with impending wakeup events.
Hence, what is needed is a mechanism for facilitating high-frequency operation of non-idle cores in conjunction with asynchronous timing events for idle cores in a multi-core processor system.